QUESTION BANK FOR MICROPROCESSORS AND MICRO CONTROLLERS

                                            PART-A
1. What are the various registers in 8085?
2. In 8085 name the 16 bit registers?
3. What are the various flags used in 8085?
4. What is Stack Pointer?
5. What is Program counter?
6. Which Stack is used in 8085?
7. What happens when HLT instruction is executed in processor?
8. What is meant by a bus?
9. What is Tri-state logic?
10. Give an example of one address microprocessor?
11. In what way interrupts are classified in 8085?
12. What are Hardware interrupts?
13. What are Software interrupts?
14. Which interrupt has the highest priority?
15. Name 5 different addressing modes?
16. How many interrupts are there in 8085?
17. What is clock frequency for 8085?
18. What is the RST for the TRAP?
19. In 8085 which is called as High order / Low order Register?
20. What are input & output devices?
21. Can an RC circuit be used as clock source for 8085?
22. Why crystal is a preferred clock source?
23. Which interrupt is not level-sensitive in 8085?
24. What does Quality factor mean?
25. What are level-triggering interrupt?
26. What is Program Counter?
Define indirect addressing mode and give an example.
What is the use of ALE signal?
List any four unconditional branch instructions
What is the use of HOLD and HLDA signals?
Write about multiplexing of 8085 address bus.
What are the various registers available in 8085?
What is the mechanism of stack?
Name the functional groups under which 8085 instructions are classified.
Compare Assembly language with High level language.
Define Assembler
How many bytes are there in the range B250H to DFFFH
What is a Flag?
What is Program Status Word?
What are the advantages of DRAM?
Define Coprocessor.
What is Assembler Directive? Give examples.
Write about salient features of 8086.
Explain how a 20 bit effective address is generated in 8086.
45.What is the purpose of MN / MX pin in 8086?
                                                    PART B
1. Draw the functional block diagram of 8085 microprocessor and explain.
2. Write a Program to Perform the following functions and verify the output steps:
(i) Load the number 5CH in register D
(ii) Load the number 9E H in register C
(iii) Increment the Contents of register C by one.
(iv) Add the contents of register C and D and Display the sum at output
port1.
3. Write an assembly language program to find out the largest number from a given
unordered array of 8 bit numbers, stored in the locations starting from a known
address.
4. With suitable examples explain 8085 instruction set in detail.
5. With suitable examples explain 8085 addressing modes in detail.
6. Explain 8085 Stack in detail.
7. Write a 8085 ALP to generate a accurate time delay of 100ms.
8. Describe Intel 8086 Microprocessor Architecture
9. Describe any five addressing modes of 8086 with suitable examples.
10. Write a 8086 ALP to convert an 8 bit binary number into equivalent gray code.
11. Explain the function of all the pins of 8085 Processor.
12. Write a 8086 ALP to sort an array of ten bytes in ascending order. Add comments
to your Program.
13. Explain the function of various flags of 8086 microprocessor.
14. Write short notes on the following multiprocessor configurations
i) Shared bus configuration ii) Multiport Memory Configurations
15 Explain the function of unsigned multiplication and Division instructions in
8086 with suitable examples.
16 With a neat block diagram, explain in detail the internal architecture of 8255
and its registers.
17. Describe the functional units present and their functions in BIU and EU of
8086.
18.What is addressing mode? Describe the addressing modes in 8085 with suitable
Examples. 8 Marks
19. Write 8085 assembly language program to SORT an array of 10 bytes in
Descending order. 8 Marks
20.Write 8086 assembly language program to perform the following
a. To move a string of words from offset 1000h to offset 6000h. The
Length of the string is 0Ch. 8 Marks
b. To add an array of bytes. The array contains 50bytes. 8 Marks
21.Explain 8085 stack in detail
                                       8086 (microprocessor):
1) How many bit 8086 microprocessor is?
2) What is the size of data bus of 8086?
3) What is the size of address bus of 8086?
4) What is the max memory addressing capacity of 8086?
5) Which are the basic parts of 8086?
6) What are the functions of BIU?
7) What are the functions of EU?
8) How many pin IC 8086 is?
9) What IC8086 is?
10) What is the size of instruction queue in 8086?
11) What is the size of instruction queue in 8088?
12) Which are the registers present in 8086?
13) What do you mean by pipelining in 8086?
14) How many 16 bit registers are available in 8086?
15) Specify addressing modes for any instruction?
16) What do you mean by assembler directives?
17) What .model small stands for?
18) What is the supply requirement of 8086?
19) What is the relation between 8086 processor frequency & crystal
frequency?
20) Functions of Accumulator or AX register?
21) Functions of BX register?
22) Functions of CX register?
23) Functions of DX register?
24) How Physical address is generated?
25) Which are pointers present in this 8086?
26) Which is by default pointer for CS/ES?
27) How many segments present in it?
28) What is the size of each segment?
29) Basic difference between 8085 and 8086?
30) Which operations are not available in 8085?
31) What is the difference between min mode and max mode of 8086?
32) What is the difference between near and far procedure?
33) What is the difference between Macro and procedure?
34) What is the difference between instructions RET & IRET?
35) What is the difference between instructions MUL & IMUL?
36) What is the difference between instructions DIV & IDIV?
37) What is difference between shifts and rotate instructions?
38) Which are strings related instructions?
39) Which are addressing modes and their examples in 8086?
40) What does u mean by directives?
41) What does u mean by Prefix?
42) What .model small means?
43) Difference between small, medium, tiny, huge?
44) What is dd, dw, db?
45) Interrupts in 8086 and there function.
46) What is the function of 01h of Int 21h?
47) What is the function of 02h of Int 21h?
48) What is the function of 09h of Int 21h?
49) What is the function of 0Ah of Int 21h?
50) What is the function of 4ch of Int 21h?
51) What is the reset address of 8086?
52) What is the size of flag register in 8086? Explain all.
53) What is the difference between 08H and 01H functions of INT 21H?
54) Which is faster- Reading word size data whose starting address is at
even or at odd address of memory in 8086?
55) Which are the default segment base: offset pairs?
56) Can we use SP as offset address holder with CS?
57) Which are the base registers in 8086?
58) Which is the index registers in 8086?
59) What do you mean by segment override prefix?
60) Whether micro reduces memory requirements?
61) What do you mean by macro?
62) What is diff between macro and procedure?
63) Types of procedure?
64) What TASM is?
65) What TLINK is?
66) What TD is?
67) What do u mean by assembler?
68) What do u mean by linker?
69) What do u mean by loader?
70) What do u mean by compiler?
71) What do u mean by emulator?
72) Stack related instruction?
73) .stack 100 means?
74) What do you mean by 20 dup (0)?
75) Which flags of 8086 are not present in 8085?
76) What is the size of flag register?
77) Can you perform 32 bit operation with 8086? How?
78) Whether 8086 is compatible with Pentium processor?
79) What is 8087? How it is different from 8086?
80) While accepting no. from user why u need to subtract 30 from that?
81) While displaying no. from user why u need to add 30 to that?
82) What are ASCII codes for nos. 0 to F?
83) How does U differentiate between positive and negative numbers?
84) What is range for these numbers?
85) Which no. representation system you have used?
86) What is LEA?
87) What is @data indicates in instruction- MOV ax, @data?
88) What is maximum size of the instruction in 8086?
89) Why we indicate FF as 0FF in program?
90) What is mul BX and div BX? Where result goes?
91) Where queue is present?
92) What is the advantage of using internal registers?
93) What is SI, DI and their functions?
94) Which are the pointers used in 8086 and their functions?
95) What is a type of queue in 8086?
96) What is minimum mode of 8086?
97) What is maximum mode of 8086?
98) Which are string instructions?
99) In string operations which is by default string source pointer?
100) In string operations which is by default string destination pointer?
                                      PROGRAMS:
1) What do you mean by assembler?
2) What do you mean by linker?
3) What do you mean by debugger?
4) What do you mean by compiler?
5) What do you mean by locator?
6) What do you mean by emulator?
7) When divide overflow error occurs?
8) What .startup stands for?
9) Explain the logic of array addition program.
10) Explain the logic of finding out negative nos. from an array of signed
nos.
11) Explain the logic of code conversion (BCD to hex and hex to BCD)
program.
12) Explain the logic of multiplication (by successive addition and shift and
add method) program.
13) Explain the logic of non overlap and overlap block transfer program
14) Explain the logic of string related programs.
15) Which assembler directives are used with near procedure?
16) Which assembler directives are used with far procedure?
                                     INTERRUPTS:
1) What do you mean by interrupt?
2) Which are the hardware and software interrupts in 8086?
3) Mention the priority of interrupts in8086.
4) What is int1, int2, int3?
5) What do you mean by NMI interrupt?
6) What do you mean by IVT in 8086?
7) What is the size of IVT?
8) Where IVT is located?
9) Which steps 8086 follows to handle any interrupt?
                       INTERFACING:
1) What are the types of interfacing?
2) Compare memory interfacing and IO interfacing.
3) What are the types of IO interfacing?
4) What is the difference between direct and indirect IO interfacing?
5) What is the difference between memory mapped IO and IO mapped IO
interfacing?
                         8255 (programmable peripheral interface) :
1) What IC 8255 is?
2) How many pin IC 8255 is?
3) Explain control word format of 8255?
1.What are the flags in 8086?
- In 8086 Carry flag, Parity flag, Auxiliary carry flag, Zero flag, Overflow flag, Trace
flag, Interrupt flag, Direction flag, and Sign flag.
2.What are the various interrupts in 8086?
- Maskable interrupts, Non-Maskable interrupts.
3.What is meant by Maskable interrupts?
- An interrupt that can be turned off by the programmer is known as Maskable interrupt.
4.What is Non-Maskable interrupts?
An interrupt which can be never be turned off (ie.disabled) is known as Non-Maskable
interrupt.
5.Which interrupts are generally used for critical events?
- Non-Maskable interrupts are used in critical events. Such as Power failure, Emergency,
Shut off etc.,
6.Give examples for Maskable interrupts?
- RST 7.5, RST6.5, RST5.5 are Maskable interrupts
7.Give example for Non-Maskable interrupts?
- Trap is known as Non-Maskable interrupts, which is used in emergency condition.
8.What is the Maximum clock frequency in 8086?
- 5 Mhz is the Maximum clock frequency in 8086.
9.What are the various segment registers in 8086?
- Code, Data, Stack, Extra Segment registers in 8086.
10.Which Stack is used in 8086?
- FIFO (First In First Out) stack is used in 8086.In this type of Stack the first stored
information is retrieved first.
11.What are the address lines for the software interrupts? -
12.What is SIM and RIM instructions?
- SIM is Set Interrupt Mask. Used to mask the hardware interrupts. RIM is Read
Interrupt Mask. Used to check whether the interrupt is Masked or not.
13.Which is the tool used to connect the user and the computer?
- Interpreter is the tool used to connect the user and the tool.
14.What is the position of the Stack Pointer after the PUSH instruction?
- The address line is 02 less than the earlier value.
15.What is the position of the Stack Pointer after the POP instruction?
- The address line is 02 greater than the earlier value.
16.Logic calculations are done in which type of registers?
- Accumulator is the register in which Arithmetic and Logic calculations are done.
17.What are the different functional units in 8086?
- Bus Interface Unit and Execution unit, are the two different functional units in 8086.
18.Give examples for Micro controller?
- Z80, Intel MSC51 &96, Motorola are the best examples of Microcontroller.
19.What is meant by cross-compiler?
- A program runs on one machine and executes on another is called as cross-compiler.
20.What are the address lines for the hardware interrupts? -
21.Which Segment is used to store interrupt and subroutine return address registers?
- Stack Segment in segment register is used to store interrupt and subroutine return
address registers.
22.Which Flags can be set or reset by the programmer and also used to control the
operation of the processor?
- Trace Flag, Interrupt Flag, Direction Flag.
23.What does EU do?
- Execution Unit receives program instruction codes and data from BIU, executes these
instructions and store the result in general registers.
24.Which microprocessor accepts the program written for 8086 without any changes?
- 8088 is that processor.
25.What is the difference between 8086 and 8088?
- The BIU in 8088 is 8-bit data bus & 16- bit in 8086.Instruction queue is 4 byte long in
8088and 6 byte in 8086.

PROGRAMS IN DIGITAL SYSTEMS AND SYSTEM DESIGN- ALTERA

PROGRAMS USING BEHAVIORAL MODELING
--------------------------------------
-- OR gate
-- two descriptions provided
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity OR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end OR_ent;
---------------------------------------
architecture OR_arch of OR_ent is
begin
process(x, y)
begin
-- compare to truth table
if ((x='0') and (y='0')) then
F <= '0';
else
F <= '1';
end if;
end process;
end OR_arch;
architecture OR_beh of OR_ent is
begin
F <= x or y;
end OR_beh;
---------------------------------------
--------------------------------------------------
-- AND gate
-- two descriptions provided
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------
entity AND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end AND_ent;
--------------------------------------------------
architecture behav1 of AND_ent is
begin
process(x, y)
begin
-- compare to truth table
if ((x='1') and (y='1')) then
F <= '1';
else
F <= '0';
end if;
end process;
end behav1;
architecture behav2 of AND_ent is
begin
F <= x and y;
end behav2;
--------------------------------------
-- XOR gate
-- two descriptions provided
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity XOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end XOR_ent;
--------------------------------------
architecture behv1 of XOR_ent is
begin
process(x, y)
begin
-- compare to truth table
if (x/=y) then
F <= '1';
else
F <= '0';
end if;
end process;
end behv1;
architecture behv2 of XOR_ent is
begin
F <= x xor y;
end behv2;
-----------------------------------------
-- NOR gate
--
-- two descriptions provided
-----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------
entity NOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end NOR_ent;
------------------------------------------
architecture behv1 of NOR_ent is
begin
process(x, y)
begin
-- compare to truth table
if (x='0' and y='0') then
F <= '1';
else
F <= '0';
end if;
end process;
end behv1;
architecture behv2 of NOR_ent is
begin
F <= x nor y;
end behv2;
-----------------------------------------
-- NAND gate
-- two descriptions provided
-----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------
entity NAND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end NAND_ent;
------------------------------------------
architecture behv1 of NAND_ent is
begin
process(x, y)
begin
-- compare to truth table
if (x='1' and y='1') then
F <= '0';
else
F <= '1';
end if;
end process;
end behv1;
-----------------------------------------
architecture behv2 of NAND_ent is
begin
F <= x nand y;
end behv2;
--------------------------------------
-- XOR gate
-- two descriptions provided
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity XNOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end XNOR_ent;
---------------------------------------
architecture behv1 of XNOR_ent is
begin
process(x, y)
begin
-- compare to truth table
if (x/=y) then
F <= '0';
else
F <= '1';
end if;
end process;
end behv1;
architecture behv2 of XNOR_ent is
begin
F <= x xnor y;
end behv2;
---------------------------------------
Example Combinational Circuit
------------------------------------------------------------
-- Combinational Logic Design
-- A simple example of VHDL Structure Modeling
-- we might define two components in two separate files,
-- in main file, we use port map statement to instantiate
-- the mapping relationship between each components
-- and the entire circuit.
------------------------------------------------------------
library ieee; -- component #1
use ieee.std_logic_1164.all;
entity OR_GATE is
port( X: in std_logic;
Y: in std_logic;
F2: out std_logic
);
end OR_GATE;
architecture behv of OR_GATE is
begin
process(X,Y)
begin
F2 <= X or Y; -- behavior des.
end process;
end behv;
-------------------------------------------------------------
library ieee; -- component #2
use ieee.std_logic_1164.all;
entity AND_GATE is
port( A: in std_logic;
B: in std_logic;
F1: out std_logic
);
end AND_GATE;
architecture behv of AND_GATE is
begin
process(A,B)
begin
F1 <= A and B; -- behavior des.
end process;
end behv;
library ieee; -- top level circuit
use ieee.std_logic_1164.all;
use work.all;
entity comb_ckt is
port( input1: in std_logic;
input2: in std_logic;
input3: in std_logic;
output: out std_logic
);
end comb_ckt;
architecture struct of comb_ckt is
component AND_GATE is -- as entity of AND_GATE
port( A: in std_logic;
B: in std_logic;
F1: out std_logic
);
end component;
component OR_GATE is -- as entity of OR_GATE
port( X: in std_logic;
Y: in std_logic;
F2: out std_logic
);
end component;
signal wire: std_logic; -- signal just like wire
begin
-- use sign "=>" to clarify the pin mapping
Gate1: AND_GATE port map (A=>input1, B=>input2, F1=>wire);
Gate2: OR_GATE port map (X=>wire, Y=>input3, F2=>output);
end struct;
-------------------------------------------------
-- VHDL code for 4:1 multiplexer
--
-- Multiplexer is a device to select different
-- inputs to outputs. we use 3 bits vector to
-- describe its I/O ports
-------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity Mux is
port( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end Mux;
-------------------------------------------------
architecture behv1 of Mux is
begin
process(I3,I2,I1,I0,S)
begin
-- use case statement
case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others => O <= "ZZZ";
end case;
end process;
end behv1;
architecture behv2 of Mux is
begin
-- use when.. else statement
O <= I0 when S="00" else
I1 when S="01" else
I2 when S="10" else
I3 when S="11" else
"ZZZ";
end behv2;
-------------------------------------------------
-- 2:4 Decoder
-- decoder is a kind of inverse process
-- of multiplexrr
-------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity DECODER is
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end DECODER;
-------------------------------------------------
architecture behv of DECODER is
begin
-- process statement
process (I)
begin
-- use case statement
case I is
when "00" => O <= "0001";
when "01" => O <= "0010";
when "10" => O <= "0100";
when "11" => O <= "1000";
when others => O <= "XXXX";
end case;
end process;
end behv;
architecture when_else of DECODER is
begin
-- use when..else statement
O <= "0001" when I = "00" else
"0010" when I = "01" else
"0100" when I = "10" else
"1000" when I = "11" else
"XXXX";
end when_else;
--------------------------------------------------------
-- VHDL code for n-bit adder
-- function of adder:
-- A plus B to get n-bit sum and 1 bit carry
-- we may use generic statement to set the parameter
-- n of the adder.
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------
entity ADDER is
generic(n: natural :=2);
port( A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
carry: out std_logic;
sum: out std_logic_vector(n-1 downto 0)
);
end ADDER;
--------------------------------------------------------
architecture behv of ADDER is
-- define a temparary signal to store the result
signal result: std_logic_vector(n downto 0);
begin
-- the 3rd bit should be carry
result <= ('0' & A)+('0' & B);
sum <= result(n-1 downto 0);
carry <= result(n);
end behv;
---------------------------------------------------
-- n-bit Comparator
-- this simple comparator has two n-bit inputs &
-- three 1-bit outputs
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
---------------------------------------------------
entity Comparator is
generic(n: natural :=2);
port( A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
less: out std_logic;
equal: out std_logic;
greater: out std_logic
);
end Comparator;
---------------------------------------------------
architecture behv of Comparator is
begin
process(A,B)
begin
if (A<B) then
less <= '1';
equal <= '0';
greater <= '0';
elsif (A=B) then
less <= '0';
equal <= '1';
greater <= '0';
else
less <= '0';
equal <= '0';
greater <= '1';
end if;
end process;
end behv;
---------------------------------------------------
-- Simple ALU Module
-- ALU stands for arithmatic logic unit.
-- It perform multiple operations according to
-- the control bits.
-- we use 2's complement subraction in this example
-- two 2-bit inputs & carry-bit ignored
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
---------------------------------------------------
entity ALU is
port( A: in std_logic_vector(1 downto 0);
B: in std_logic_vector(1 downto 0);
Sel: in std_logic_vector(1 downto 0);
Res: out std_logic_vector(1 downto 0)
);
end ALU;
---------------------------------------------------
architecture behv of ALU is
begin
process(A,B,Sel)
begin
-- use case statement to achieve
-- different operations of ALU
case Sel is
when "00" =>
Res <= A + B;
when "01" =>
Res <= A + (not B) + 1;
when "10" =>
Res <= A and B;
when "11" =>
Res <= A or B;
when others =>
Res <= "XX";
end case;
end process;
end behv;
----------------------------------------------------
--------------------------------------------------------
-- Example of doing showing
-- (1) how to use variable with in process
-- (2) how to use for loop statement
-- (3) algorithm of multiplication
--
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- two 4-bit inputs and one 8-bit outputs
entity multiplier is
port( num1, num2: in std_logic_vector(1 downto 0);
product: out std_logic_vector(3 downto 0)
);
end multiplier;
architecture behv of multiplier is
begin
process(num1, num2)
variable num1_reg: std_logic_vector(2 downto 0);
variable product_reg: std_logic_vector(5 downto 0);
begin
num1_reg := '0' & num1;
product_reg := "0000" & num2;
-- use variables doing computation
-- algorithm is to repeat shifting/adding
for i in 1 to 3 loop
if product_reg(0)='1' then
product_reg(5 downto 3) := product_reg(5 downto 3)
+ num1_reg(2 downto 0);
end if;
product_reg(5 downto 0) := '0' & product_reg(5 downto 1);
end loop;
-- assign the result of computation back to output signal
product <= product_reg(3 downto 0);
end process;
end behv;
Simple D Latch
-- latch is simply controlled by enable bit
-- but has nothing to do with clock sigal
-- notice this difference from flip-flops
--------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
--------------------------------------------
entity D_latch is
port( data_in: in std_logic;
enable: in std_logic;
data_out: out std_logic
);
end D_latch;
--------------------------------------------
architecture behv of D_latch is
begin
-- compare this to D flipflop
process(data_in, enable)
begin
if (enable='1') then
-- no clock signal here
data_out <= data_in;
end if;
end process;
end behv;
-- ---------------------------------------------
-- D Flip-Flop
--
-- Flip-flop is the basic component in
-- sequential logic design
-- we assign input signal to the output
-- at the clock rising edge
---------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use work.all;
---------------------------------------------
entity dff is
port( data_in: in std_logic;
clock: in std_logic;
data_out: out std_logic
);
end dff;
----------------------------------------------
architecture behv of dff is
begin
process(data_in, clock)
begin
-- clock rising edge
if (clock='1' and clock'event) then
data_out <= data_in;
end if;
end process;
end behv;
----------------------------------------------
----------------------------------------------
-- JK Flip-Flop with reset
--
--
-- the description of JK Flip-Flop is based
-- on functional truth table
-- concurrent statement and signal assignment
-- are using in this example
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------
entity JK_FF is
port ( clock: in std_logic;
J, K: in std_logic;
reset: in std_logic;
Q, Qbar: out std_logic
);
end JK_FF;
-----------------------------------------------
architecture behv of JK_FF is
-- define the useful signals here
signal state: std_logic;
signal input: std_logic_vector(1 downto 0);
begin
-- combine inputs into vector
input <= J & K;
p: process(clock, reset) is
begin
if (reset='1') then
state <= '0';
elsif (rising_edge(clock)) then
-- compare to the truth table
case (input) is
when "11" =>
state <= not state;
when "10" =>
state <= '1';
when "01" =>
state <= '0';
when others =>
null;
end case;
end if;
end process;
-- concurrent statements
Q <= state;
Qbar <= not state;
end behv;
-------------------------------------------------
---------------------------------------------------
-- n-bit Register
--
-- KEY WORD: concurrent, generic and range
---------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------
entity reg is
generic(n: natural :=2);
port( I: in std_logic_vector(n-1 downto 0);
clock: in std_logic;
load: in std_logic;
clear: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end reg;
----------------------------------------------------
architecture behv of reg is
signal Q_tmp: std_logic_vector(n-1 downto 0);
begin
process(I, clock, load, clear)
begin
if clear = '0' then
-- use 'range in signal assigment
Q_tmp <= (Q_tmp'range => '0');
elsif (clock='1' and clock'event) then
if load = '1' then
Q_tmp <= I;
end if;
end if;
end process;
-- concurrent statement
Q <= Q_tmp;
end behv;
---------------------------------------------------
---------------------------------------------------
-- 3-bit Shift-Register/Shifter
--
--
-- reset is ignored according to the figure
---------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
---------------------------------------------------
entity shift_reg is
port( I: in std_logic;
clock: in std_logic;
shift: in std_logic;
Q: out std_logic
);
end shift_reg;
---------------------------------------------------
architecture behv of shift_reg is
-- initialize the declared signal
signal S: std_logic_vector(2 downto 0):="111";
begin
process(I, clock, shift, S)
begin
-- everything happens upon the clock changing
if clock'event and clock='1' then
if shift = '1' then
S <= I & S(2 downto 1);
end if;
end if;
end process;
-- concurrent assignment
Q <= S(0);
end behv;
----------------------------------------------------
-- VHDL code for n-bit counter
--
-- this is the behavior description of n-bit counter
-- another way can be used is FSM model.
----------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
----------------------------------------------------
entity counter is
generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;
----------------------------------------------------
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0);
begin
-- behavior describe the counter
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Pre_Q;
end behv;
-----------------------------------------------------

MICRO CONTROLLER-EXPERIMENTS-8051

ADDITION
MOV R0,#00
MOV A,#DATA1
ADD A, #DATA2
JNC LABEL
INC R0
LABEL: MOV DPTR,#4150
MOVX @DPTR,A
INC DPTR
MOV A,R0
MOVX @DPTR,A
HERE: SJMP HERE




SUBTRACTION
CLR C
MOV B,#00
MOV A,#DATA1
SUBB A,#DATA2
JNC LABEL
CPL A
INC A
INC B
LABEL: MOV DPTR,#4150
MOVX @DPTR, A
INC DPTR
MOV A,B
MOVX @DPTR,A
HERE: SJMP HERE




MULTIPLICATION
MOV A, #DATA1
MOV B, A
MOV A, #DATA2
MUL AB
MOV DPTR, #4150
MOVX @DPTR, A
INC DPTR
MOV A, B
MOVX @DPTR, A
LOOP: SJMP LOOP




DIVISION
MOV A, #DATA1
MOV B,A
MOV A, #DATA2
DIV AB
MOV DPTR, #4150
MOVX @DPTR, A
INC DPTR
MOV A, B
MOV @DPTR, A
LOOP SJMP LOOP




INTERFACING OF DAC (Digital to Analog Converter)
GENERATING WAVEFORMS:-


SQUARE WAVE GENERATION
START MOV DPTR,#FFC8
MOV A,#00
MOVX @DPTR,A
LCALL DELAY
MOV A,#FF
MOVX @DPTR,A
LCALL DELAY
LJMP START
DELAY MOV R1, #05
LOOP MOV R2, #FF
HERE DJNZ R2, HERE
DJNZ R1, LOOP
RET


SAWTOOTH WAVEFORM
MOV DPTR, #FFC8
MOV A,#00
LOOP: MOVX @DPTR,A
INC A
SJMP LOOP


TRIANGULAR WAVEFORM
MOV DPTR, #FFC8
START MOV A, #00
LOOP1 MOV @DPTR,A
INC A
JNZ LOOP1
MOV A, #FF
LOOP2 MOVX @DPTR,A
DEC A
JNZ LOOP2
LJMP START


STEPPER MOTOR
Start: MOV DPTR,#4500
MOV R0,#04H
JO : MOVX A,@DPTR
PUSH DPH
PUSH DPL
MOV DPTR,#FFC0
MOV R2,#04
MOV R1,#0F
DLY1: MOV R3,#0F
DLY: DJNZ R3,DLY
DJNZ R1,DLY1
DJNZ R2,DLY1
MOVX @DPTR,A
POP DPL
POP DPH
INC DPTR
DJNZ R0,JO
SJMP START


Address            For Clockwise Rotation           For Anticlockwise Rotation
 4500                                 08                                        08       
 4501                                 01                                        02       
 4502                                 04                                        04        
 4503                                 02                                        01       

MICRO PROCESSOR PROGRAMS-8085

PROGRAM-1-SUM OF "N" NUMBERS:-

               LDA 4200H

              MOV C, A             : Initialize counter

              SUB A                    : sum = 0

              LXI H, 420l           : Initialize pointer

BACK:ADD M                   : SUM = SUM + data

             INX H                     : increment pointer

             DCR C                    : Decrement counter

            JNZ BACK             : if counter 0 repeat

            STA 4300H              : Store sum

             HLT                           : Terminate program execution

PROGRAM-2:-

                 MOV C, A                 : Initialize counter

                 LXI H, 4201H          : Initialize pointer

                 SUB A                     :Sum low = 0

                MOV B, A                  : Sum high = 0

BACK:   ADD M                        : Sum = sum + data

               JNC SKIP

               INR B                          : Add carry to MSB of SUM

SKIP:  INX H                           :Increment pointer

             DCR C                          : Decrement counter

            JNZ BACK                   : Check if counter 0 repeat

            STA 4300H                   : Store lower byte

            MOV A, B

            STA 4301H                    : Store higher byte

             HLT                               :Terminate program execution

PROGRAM-3-SORTING THE ELEMENTS OF THE ARRAY:-

                  MVI B, 09          : Initialize counter

START: LXI H, 2200H     :Initialize memory pointer 

                 MVI C, 09H         : Initialize counter 2

BACK:    MOV A, M           : Get the number

                   INX H                   : Increment memory pointer

                  CMP M                   : Compare number with next number

                  JC SKIP                 : If less, don't interchange

                  JZ SKIP                  : If equal, don't interchange

                  MOV D, M

                  MOV M, A

                  DCX H

                  MOV M, D

                   INX H                    : Interchange two numbers

SKIP:       DCR C                    : Decrement counter 2

                  JNZ BACK              : If not zero, repeat

                  DCR B                       : Decrement counter 1

                  JNZ START

                  HLT                           : Terminate program execution

PROGRAM-4-COUNT THE NUMBER OF 1's IN A STRING:-

               MVI B, 00H

               MVI C, 08H

               MOV A, D

 BACK: RAR

              JNC SKIP

               INR B

SKIP:   DCR C

               JNZ BACK

               HLT

PROGRAM-5-FIND THE SQUARE ROOT:-

               LDA 4200H     : Get the given data(Y) in A register

               MOV B,A         : Save the data in B register

               MVI C,02H       : Call the divisor(02H) in C register

               CALL DIV         : Call division subroutine 

                                                 to get initial value(X) in D-reg

REP:    MOV E,D            : Save the initial value in E-reg

               MOV A,B            : Get the dividend(Y) in A-reg

               MOV C,D            : Get the divisor(X) in C-reg

                CALL DIV         : Call division subroutine 

                                                    to get initial value(Y/X) in D-reg

                MOV A, D            : Move Y/X in A-reg

                ADD E                   : Get the((Y/X) + X) in A-reg

                MVI C, 02H           : Get the divisor(02H) in C-reg

                CALL DIV          : Call division subroutine to 

                                                   get ((Y/X) + X)/2 in D-reg.This is XNEW

                MOV A, E             : Get Xin A-reg

                CMP D                    : Compare X and XNEW

               JNZ REP                 : If XNEW is not equal to X, then repeat

                STA 4201H             : Save the square root in memory

                HLT                          : Terminate program execution

Subroutine Program:

DIV:      MVI D, 00H               : Clear D-reg for Quotient

NEXT:  SUB C                         : Subtract the divisor from dividend

                INR D                          : Increment the quotient

                CMP C                         : Repeat subtraction until the

                JNC NEXT                 : divisor is less than dividend

                RET                                : Return to main program

PROGRAM-6-SQUARE OF THE GIVEN NUMBER:-

• LXI H, 6200H : Initialize lookup table pointer
• LXI D, 6100H : Initialize source memory pointer
• LXI B, 7000H : Initialize destination memory pointer
• BACK: LDAX D : Get the number
• MOV L, A : A point to the square
• MOV A, M : Get the square
• STAX B : Store the result at destination memory location
• INX D : Increment source memory pointer
• INX B : Increment destination memory pointer
• MOV A, C
• CPI 05H : Check for last number
• JNZ BACK : If not repeat
• HLT : Terminate program execution

PROGRAM-7-SUM OF ODD NUMBERS:-

            LDA 2200H

• MOV C, A : Initialize counter
• LXI H, 2201H : Initialize pointer
• MVI E, 00 : Sum low = 0
• MOV D, E : Sum high = 0
• BACK: MOV A, M : Get the number
• ANI 0lH : Mask Bit 1 to Bit7
• JZ SKIP : Don't add if number is even
• MOV A, E : Get the lower byte of sum
• ADD M : Sum = sum + data
• MOV E, A : Store result in E register
• JNC SKIP
• INR D : Add carry to MSB of SUM
• SKIP: INX H : Increment pointer

PROGRAM-8-TO ADD TWO 8-BIT DATA

        LDA 000

MOV B,A

LDA 001

MVI C,00

ADD B

JNC AHEAD

INR C

[lab1] STA 002

MOV A,C

STA 003

HLT

PROGRAM-9- TO ADD TWO 8-BIT DATA PRESENT IN THE MEMORY

        

        LXI H,000

MVI C,OO

MOV A,M

INX H

ADD M

JNC LAB1

INR C

[LAB1] INX H

MOV M,A

INX H

MOV M,C

HLT

PROGRAM-10- TO ADD TWO 16-BIT DATA:-

LHLD 000

XCHG

LHLD 002

XRA A

DAD D

JNC LAB1

INR A

[LAB1] SHLD 004

STA 006

HLT

PROGRAM-11-TO SUBTRACT TWO 16-BIT DATA:-

LDA 002

MOV B,A

LDA 000

SUB B

STA 004

LDA 003

MOV B,A

LDA 001

SBB

STA 005

HLT

PROGRAM-12-TO ADD TWO 2-DIGIT BCD DATA:-

LDA 000

MOV B,A

LDA 001

MIV C,00

ADD D

DAA

JNC LAB1

INR C

[LAB1] STA 002

MOV A,C

STA 003

HLT

PROGRAM-13-TO ADD TWO 4-DIGIT BCD DATA:-

LDA 000

MOV B,A

LDA 002

MVI C,00

ADD B

DAA

STA 004

LDA 001

MOV B,A

LDA 003

ADC B

DAA

STA 005

JNC GO

INR C

[GO] MOV A,C

STA 006

HLT

PROGRAM-14-TO MULTIPLY TWO NUMBERS OF 8-BIT DATA:-

LXI H,000

MVI C,00

XRA A

MOV B,M

INX H

MOV D,M

[REPT] ADD D

JNC GO

INR C

[GO] DCR B

JNZ REPT

INX H

MOV M,A

INX H

MOV M,C

HLT

PROGRAM-15-TO MULTIPLY TWO NUMBERS OF 16-BIT DATA:-

LHLD 000

SPHL

LHLD 002

XCHG

LXI H,000

LXI B,000

[NEXT] DAD SP

JNC AHED

INX B

[AHED] DCX D

MOV A,E

ORA D

JNZ NEXT

SHLD 004

MOV L,C

MOV H,B

SHLD 006

HLT

PROGRAM-16-TO DIVIDE TWO NUMBERS OF 8-BIT DATA

LDA 001

MOV B,A

LDA 000

MVI C,00

[AGO] CMP B

JC STORE

SUB B

INR C

JMP AGO

[STO] STA 003

MOV A,C

STA 002

HLT

PROGRAM-17-TO ADD AN ARRAY OF DATA:-

LXI H,000

MOV B,M

MVI C,00

XRA A

[REPT] INX H

ADD M

JNC AH1

INR C

[AH1] DCR B

JNZ REPT

STA 100

MOV A,C

STA 101

HLT

PROGRAM-18-TO SEARCH SMALLEST DATA IN THE ARRAY:-

LXI H,000

MOV B,M

INX H

MOV A,M

DCR B

[LOOP] INX H

CMP M

JC AHED

MOV A,M

[AHD] DCR B

JNZ LOOP

STA 100

HLT

PROGRAM-19-TO SEARCH LARGEST DATA IN THE ARRAY:-

LXI H,000

MOV B,M

INX H

MOV A,M

DCR B

[LOOP] INX H

CMP M

JNC AHED

MOV A,M

[AHED] DCR B

JNZ LOOP

STA 100

HLT

PROGRAM-20-TO SORT AN ARRAY OF DATA IN ASCENDING ORDER:-

LDA 000

MOV B,A

DCR B

[LOP2] LXI H,100

MOV C,M

DCR C

[LOP1] INX H

MOV A,M

INX H

CMP M

JC AHD1

MOV D,M

MOV M,A

DCX H

MOV M,D

JMP AHED

[AHD1] DCX H

[AHED] DCR C

JNZ LOP1

DCR B

JNZ LOP2

HLT

PROGRAM-21-TO SORT AN ARRAY OF DATA IN DESCENDING ORDER

LDA 000

MOV B,A

DCR B

[LOP2] LXI H,100

MOV C,M

DCR C

[LOP1] INX H

MOV A,M

INX H

CMP M

JNC AHD1

MOV D,M

MOV M,A

DCX H

MOV M,D

JMP AHED

[AHD1] DCX H

[AHED] DCR C

JNZ LOP1

DCR B

JNZ LOP2

HLT

PROGRAM-22-TO FIND THE SQUARE ROOT OF AN 8-BIT BINARY NUMBER

LDA 000

MOV B,A

MVI C,02

CALL DIV

[REPT] MOV E,D

MOV A,M

MOV C,D

CALL DIV

MOV A,D

ADD E

MVI C,02

CALL DIV

MOV A,E

CMP D

JNZ REPT

STA 001

HLT

[DIV] MOV D,00

[NEXT] SUB C

INR D

CMP C

JNC NEXT

RET

PROGRAM-23-TO CONVERT 2 DIGIT BCD TO BINARY NUMBER

LDA 000

MOV E,A

ANI F0

RLC

RLC

RLC

RLC

MOV B,A

XRA A

MVI C,0A

[REPT] ADD B

DCR C

JNZ REPT

MOV B,A

MOV A,E

ANI 0F

ADD B

STA 100

HLT

PROGRAM-24-TO CONVERT 8-BIT BINARY NUMBER TO BCD

MVI E,00

MOV D,E

LDA 000

[HUND] CPI 64

JC TEN

SUI 64

INR E

JMP HUND

[TEN] CPI 0A

JC UNIT

SUI 0A

INR D

JMP TEN

[UNIT] MOV C,A

MOV A,D

RLC

RLC

RLC

RLC

ADD C

STA 250

MOV A,E

STA 251

HLT

PROGRAM-25-TO CONVERT 8-BIT BINARY TO ASCII

LDA 000

MOV B,A

ANI 0F

CALL CODE

STA 001

MOV A,B

ANI F0

RLC

RLC

RLC

RLC

CALL CODE

STA 002

HLT

[CODE] CPI 0A

JC SKIP

ADI 07

[SKIP] ADI 30

RET

PROGRAM-26-TO CONVERT ASCII CODE' TO BINARY VALUE

LXI H,000

MOV D,M

LXI B,100

[LOOP] INX H

MOV A,M

CALL BIN

STAX B

INX B

DCR D

JNZ LOOP

HLT

[BIN] SUI 30

CPI 0A

RC

SUI 07

RET

                                        ALL THE BEST!!!!!!